Many digital interfaces employ a system in which a parameter is created by a transmitting party according to a predetermined formula and a required audio clock is regenerated from a transmitted clock by using the parameter. As a typical structure of this system, a digital PLL is used by itself or in combination with an analog PLL.
It has been common in the art to use a transmitted clock as an operation clock of a digital PLL for regenerating a clock (e.g., see Non-patent document 1).
FIG. 7 is a block diagram showing a structure of a conventional digital PLL device.
The conventional digital PLL device of FIG. 7 includes an n dividing unit 1, a phase comparing unit 2, an oscillating unit 3, and an m dividing unit 4.
As shown in FIG. 7, the n dividing unit 1 frequency-divides a clock transmitted through a digital interface by n to produce a digital PLL reference signal. The phase comparing unit 2 operates by using the transmitted clock as an operation clock. The phase comparing unit 2 obtains the phase difference between the reference signal generated by the n dividing unit 1 and a comparison signal generated by dividing an output clock by m in the m dividing unit 4, and outputs a control signal so as to reduce the phase difference. The oscillating unit 3 changes the output clock by the control signal received from the phase comparing unit 2. This operation is repeated as a feedback loop, whereby the phase of the output clock is caused to track (lock to) the phase of the reference signal.
For example, in an HDMI specification, parameters N and CTS are prepared as parameters for regenerating an audio clock. These parameters are defined by the following formula:CTS=(transmitted clock×N)/(128×Fs)where Fs (Sampling Frequency) indicates an audio clock.
A source device as a transmitter determines the value of CTS by counting the number of transmitted clocks in each of the (128×Fs/N) clocks. A sink device as a receiver frequency-divides the transmitted clock by CTS to generate a digital PLL reference signal. By repeating an operation of comparing the phase of a comparison signal generated by frequency-dividing an output signal by N with the phase of the generated reference signal and controlling the output clock so that the phase difference becomes zero, the phase of the comparison signal is caused to track the phase of the reference signal. By thus locking the output clock to (128×Fs), Fs can be regenerated by the sink device.
Non-patent document 1: High-Definition Multimedia Interface Specification Version 1.3a